1. Field of the Invention
This invention relates generally to semiconductor devices, and more particularly, to electrically erasable programmable read only memory (xe2x80x9cEEPROMxe2x80x9d) cells.
2. Description of the Related Art
The trend in construction of Electrically Erasable Programmable Read Only Memory (EEPROM) cells follows the general trend of semiconductor process technology in the move toward defining smaller device features. Non-volatile memory device designers strive to increase the performance of devices, while decreasing device dimensions and consequently increasing circuit density. In addition, in EEPROM devices used for programmable logic devices, designers strive to reduce power requirements of devices by reducing program and erase voltage requirements. Generally, arrays of individual memory cells are formed on a single substrate and combined with sense and read circuitry, and connected by row-wise and column-wise conductive regions or metallic conductors to allow for array wide bulk program and erase as well as selected bit programming.
In the past, conventional EEPROMs used xe2x80x9cstacked gatexe2x80x9d (or dual-poly) cells, wherein multiple applications of polysilicon formation were required to build cell structures. Recently, the conventional xe2x80x9cstacked gatexe2x80x9d EEPROM structure has given way to different cell designs and array architectures, all intended to increase density and reliability in the resulting circuit. Stacked gate devices utilizing Fowler-Nordheim tunneling to program and erase the floating gate gave way to single-layer polysilicon-based cells such as that set forth in U.S. Pat. No. 4,924,278, a schematic of which is shown in FIG. 1.
The EEPROM structure disclosed therein utilizes a single layer of polycrystalline silicon and a control gate formed in the silicon substrate to eliminate the need to form a separate control gate and floating gate in two layers of polysilicon. The EEPROM structure is made up of three separate NMOS transistors: a write transistor, a read transistor, and a sense transistor. In order to give the floating gate a positive charge (program) or negative charge (erase), electron tunneling, for example using the well-known Fowler-Nordheim tunneling technique, may be performed by applying the appropriate voltage potentials between the floating gate and a region, such as a drain region, of a transistor. Upon applying the appropriate voltage potentials, electron tunneling occurs through a tunnel oxide layer between the floating gate and the region.
An exemplary method of programming, erasing and writing to the cell in FIG. 1 is given by Table 1:
As the feature sizes of EEPROM cells are scaled downward, the three-transistor EEPROM cells exhibit certain scalability, cost and reliability limitations. First, since three transistors (write, sense and read) form the typical EEPROM cell, the size of the EEPROM cell is large. Also, with a three-transistor cell, three oxide layers are needed that may vary in thicknesses requiring complex process steps to form the three tunnel oxide layers of varying thicknesses. Second, the manufacturing process for a smaller EEPROM cell becomes more complex and, accordingly, manufacturing costs rise as transistor channel lengths are reduced. For example, as the channel length of a transistor of the EEPROM cell is scaled downward, the thickness of the gate oxide overlying the channel must also be reduced since the gate oxide thickness must be scaled with the channel length. In view of the fact that EEPROM cells already have a complex process to form multiple oxide thicknesses, additional oxide thicknesses for the transistors would add additional steps to further complicate the manufacturing process and thereby increase manufacturing costs.
Alternative embodiments to the single poly EEPROM cell wherein the cell designers strove to achieve a two-transistor cell are also known. In such embodiments, a separate tunnel path is required to remove electrons from the floating gate of the cell. However, in such embodiments, the separate tunnel path is not optimized for tunneling though the use of doping technologies in the construction of the cell. In alternative embodiments, tunneling over an entire channel is used.
In both such embodiments, one portion of the structure which is critical to performance is the oxide through which electrons tunnel onto and off of the floating gate. Degradation in the oxide due to performance or in the manufacturing process will adversely affect the ability of the device to store charge. One of the most critical areas of oxide performance is over the program junction region where electrons are added to and removed from the floating gate. The aforementioned cell structures require, in a number of embodiments, a minimum oxide thickness of about 90-100 Angstroms for the program junction oxide region due to the presence of the relatively high electric field across the oxide during the life of the cell.
Any number of solutions have been adopted for increasing the integrity of the gate oxide regions. Development efforts in EEPROM device technology have focused on increasing the programming speed, lowering programming voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions. Many of the foregoing research goals can be addressed through development of materials and processes for the fabrication of the floating-gate electrode.
Over time, the EEPROM memory cell will be written and erased repeatedly as data is stored and removed from the memory cell. Since the EEPROM memory cell relies on charge exchange between the substrate and the floating-gate electrode, considerable stress is placed on the tunnel oxide underlying the floating-gate electrode. The charge-induced stress in the tunnel oxide can cause charge trapping sites to form within the tunnel oxide. The formation of these charge trapping sites is undesirable because, once formed, electrical current can leak through the tunnel oxide layer from the floating-gate electrode to the substrate. When charge leaks off the floating-gate electrode a data error occurs in the EEPROM memory cell.
One solution to the tunnel oxide leakage problem is to form thicker oxide layers within the EEPROM device. By providing more oxide, the formation of a small number of charged trapping sites can be tolerated without deleterious current leakage in the device. While fabricating the oxide layers to greater thicknesses reduce charge leakage problems, the thicker oxide layers prevent scaling of the overall size of the EEPROM memory cell. However, scaling down (reducing component size) of transistors having large oxide thicknesses cannot be achieved due to basic device physics.
Another problem associated with EEPROM devices having relatively thick oxide layers relates to programming and erasing speed. As the thickness of the oxide layers increase, especially the tunnel oxide, the time required to transfer a charge between the substrate and the floating-gate electrode also increases due to a reduction of tunneling currents under the same applied voltages.
The invention, roughly described, comprises an EEPROM cell having improved programming and erase characteristics. In this embodiment, the EEPROM may include a sense transistor and a select transistor, each having a first active region formed in a substrate, and sharing a second active region. The EEPROM cell may also include a floating gate having a first portion forming a gate region for said sense transistor, and a second portion overlying the second active region and forming a program junction with said second active region. In this embodiment, the first portion of said floating gate has a concentration of an impurity greater than a concentration of said impurity in the second portion of the floating gate. The EEPROM may further include a control region formed in the substrate and underlying a third portion of said floating gate.
In an alternative embodiment, the invention comprises a memory cell having improved programming performance. The cell may include a floating gate having at least a first region with a first impurity concentration and a second region with a second impurity concentration different from said first impurity concentration. The cell also includes a first active region formed in a substrate, a control gate formed adjacent to said first active region; and a second active region formed in the substrate adjacent to said control gate and said second active region. The second active region includes a program junction region underlying said first region of said floating gate.
In yet another embodiment, a method of fabricating a memory cell is provided. The method may include the steps of: forming active regions in a semiconductor substrate having a floating gate overlying at least portions of said active regions to construct at least a first and a second tunneling regions; masking a first portion of said floating gate region forming said at least first tunneling region; implanting a dopant having a concentration of an impurity into said floating gate; and removing said mask.
In a unique aspect of this method, the mask used is that which is typically used during manufacture of complementary devices formed on a single integrated circuit such that additional masking steps need not be used in implementing the invention.